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LNS Hardware Acceleration

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  • by David Spuler, Ph.D.

LNS Hardware Acceleration

Much research has gone into accelerating LNS operations, particularly LNS addition, with hardware algorithms. Papers on the use of the LNS in hardware-accelerated implementations include:

  1. Manik Chugh; Behrooz Parhami, 2013, Logarithmic Arithmetic as an Alternative to Floating-Point: a Review, Proc. 47th Asilomar Conf. Signals, Systems, and Computers (November 2013), https://ieeexplore.ieee.org/document/6810472, PDF: https://web.ece.ucsb.edu/~parhami/pubs_folder/parh13-asilo-log-arith-as-alt-to-flp.pdf (A survey paper covering the use of LNS in custom accelerated hardware implementations.)
  2. F.J. Taylor, 1983, An Extended Precision Logarithmic Number System, IEEE Trans. Acoustics, Speech, and Signal Processing (1983), https://ieeexplore.ieee.org/document/910929
  3. Parhami B., 2020, Computing with logarithmic number system arithmetic: Implementation methods and performance benefits, Comput Electr Eng 87:106800. https://doi.org/10.1016/j.compeleceng.2020.106800, https://www.sciencedirect.com/science/article/abs/pii/S0045790620306534
  4. Gautschi M, Schaffner M, Gürkaynak FK, Benini L, 2016. 4.6 A 65nm CMOS 6.4-to-29.2 pJ/FLOP@ 0.8 V shared logarithmic floating-point unit for acceleration of nonlinear function kernels in a tightly coupled processor cluster, 2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016. IEEE, pp 82–83. https://doi.org/10.1109/ISSCC.2016.7417917, https://ieeexplore.ieee.org/document/7417917
  5. Coleman JN, Softley CI, Kadlec J, Matousek R, Tichy M, Pohl Z, Hermanek A, Benschop NF, 2008, The European logarithmic microprocessor, IEEE Trans Comput 57(4):532–546. https://doi.org/10.1109/TC.2007.70791 https://ieeexplore.ieee.org/document/4358243 (A European project for LNS in hardware called the European logarithmic microprocessor or ELM.)
  6. Coleman JN, Chester E, Softley CI, Kadlec J, 2000, Arithmetic on the European logarithmic microprocessor, IEEE Trans Comput 49(7):702–715. https://doi.org/10.1109/12.863040, https://ieeexplore.ieee.org/document/863040 (More about the European project for LNS in hardware.)
  7. S. Huang, L.-G. Chen and T.-H. Chen, 1994, The chip design of a 32-b Logarithmic Number System, Proc. of ISCAS94, May 1994, https://ieeexplore.ieee.org/document/409224, PDF: http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910032469/1/00409224.pdf (Theory of a chip design for 32-bits LNS.)
  8. D. Lewis and L. Yu, 1989, Algorithm design for a 30 bit integrated logarithmic processor, Proc. of 9th Symp. on Computer Arithmetic, pp. 192-199, 1989. https://ieeexplore.ieee.org/document/72826 (30-bit LNS hardware.)
  9. T. Stouraitis and F. Taylor, 1988, Analysis of Logarithmic Number System processors, IEEE Transactions on Circuits and Systems, vol. 35, pp. 519-527, May 1988. https://ieeexplore.ieee.org/document/1779
  10. T. Stouraitis, S. Natarajan and F. Taylor, 1985, A reconfiguration systolic primitive processor for signal processing, IEEE Int. Conf. on ASSP, March 1985, https://ieeexplore.ieee.org/document/1168508
  11. Krishnendu Mukhopadhyaya, 1995, Implementation of Four Common Functions on an LNS CoProcessor, IEEE Transactions on Computers, https://ieeexplore.ieee.org/document/367997, PDF: https://www.isical.ac.in/~krishnendu/LNS-IEEE-TC.pdf
  12. Durgesh Nandan; Jitendra Kanungo; Anurag Mahajan, 2017, An efficient VLSI architecture for iterative logarithmic multiplier, 2017 4th International Conference on Signal Processing and Integrated Networks (SPIN), February 2017, https://ieeexplore.ieee.org/document/8049986 (Uses LNS and Mitchell's approximate multiplication algorithm.)
  13. Durgesh Nandan, Jitendra Kanungo, Anurag Mahajan, 2017, An Efficient VLSI Architecture Design for Logarithmic Multiplication by Using the Improved Operand Decomposition, In: Integration, Volume 58, June 2017, Pages 134-141, https://doi.org/10.1016/j.vlsi.2017.02.003, https://www.sciencedirect.com/science/article/abs/pii/S0167926017300895 (Uses LNS and Mitchell's approximate multiplication algorithm.)
  14. Siti Zarina Md Naziri; Rizalafande Che Ismail; Ali Yeon Md Shakaff, 2014, The Design Revolution of Logarithmic Number System Architecture, 2014 2nd International Conference on Electrical, Electronics and System Engineering (ICEESE), DOI: 10.1109/ICEESE.2014.7154603, https://doi.org/10.1109/ICEESE.2014.7154603, https://ieeexplore.ieee.org/document/7154603
  15. J. N. Coleman and E. I. Chester, 1999, A 32-Bit Logarithmic Arithmetic Unit and Its Performance Compared to Floating-Point, Proc. 14th IEEE Symp. Computer Arithmetic, 1999, pp. 142-151, https://ieeexplore.ieee.org/document/762839 (32-bit arithmetic in an early European project for LNS in hardware.)
  16. F. J. Taylor, R. Gill, J. Joseph, and J. Radke, 1988, A 20 Bit Logarithmic Number System Processor, IEEE Trans. Computers, Vol. 37, pp. 190-200, 1988. https://ieeexplore.ieee.org/document/2148 (A 1988 hardware 20-bit version of logarithmic numbers.)
  17. J. N. Coleman, C. I. Softley, J. Kadlec, R. Matousek, M. Licko, Z. Pohl, and A. Hermanek, 2003, Performance of the European Logarithmic Microprocessor, Proc. SPIE Annual Meeting, 2003, pp. 607-617. https://www.semanticscholar.org/paper/Performance-of-the-European-logarithmic-Coleman-Softley/7a324cd01bd1f4a25d70dfe6875474c9b92a3d9c
  18. Haohuan Fu; Oskar Mencer; Wayne Luk, 2006, Comparing Floating-Point and Logarithmic Number Representations for Reconfigurable Acceleration, 2006 IEEE International Conference on Field Programmable Technology, https://ieeexplore.ieee.org/document/4042464 (Evaluates LNS vs floating-point for FPGAs.)
  19. J.N. Coleman; C.I. Softley; J. Kadlec; R. Matousek; M. Licko; Z. Pohl; A. Hermanek, 2001, The European Logarithmic Microprocessor - a QR RLS application, Engineering, Computer Science Conference Record of Thirty-Fifth Asilomar… 2001 https://ieeexplore.ieee.org/document/986897
  20. H. Kim; B.-G. Nam; J.-H. Sohn; J.-H. Woo; H.-J. Yoo, 2006, A 231-MHz, 2.18-mW 32-bit Logarithmic Arithmetic Unit for Fixed-Point 3-D Graphics System, IEEE J. Solid-State Circuits (Volume 41, Issue 11, November 2006) https://ieeexplore.ieee.org/document/1717660
  21. T. Stouraitis, 1989, A hybrid floating-point/logarithmic number system digital signal processor, Int. Conf. Acoust. Speech Signal Process., 1989. https://ieeexplore.ieee.org/document/266619
  22. I. Kouretas and V. Paliouras, 2018, Logarithmic number system for deep learning, in International Conference on Modern Circuits and Systems Technologies (MOCAST). IEEE, 2018, pp. 1–4, https://ieeexplore.ieee.org/abstract/document/8376572
  23. J. H. Lang, C. A. Zukowski, R. O. LaMaire, and C. H. An, 1985, Integrated-Circuit Logarithmic Units, IEEE Trans. Computers, Vol. 34, pp. 475-483, 1985. https://ieeexplore.ieee.org/document/1676588 (Hardware version of logarithmic numbers from 1985.)
  24. D. Yu and D. M. Lewis, 1991, A 30-b Integrated Logarithmic Number System Processor, IEEE J. Solid-State Circuits, Vol. 26, pp. 1433-1440, 1991. https://www.scribd.com/document/41667733/A-30-b-Integrated-Logarithmic-Number-System-Processor-91 (An early 1991 hardware version of LNS with 30-bits.)
  25. V. Paliouras, J. Karagiannis, G. Aggouras, and T. Stouraitis, 1998, A Very-Long Instruction Word Digital Signal Processor Based on the Logarithmic Number System, Proc. 5th IEEE Int’l Conf. Electronics, Circuits and Systems, Vol. 3, pp. 59-62, 1998. https://ieeexplore.ieee.org/document/813936 (A hardware version of LNS from 1998.)
  26. M. G. Arnold, 2003, A VLIW Architecture for Logarithmic Arithmetic, Proc. Euromicro Symp. Digital System Design, 2003, pp. 294-302. https://ieeexplore.ieee.org/document/1231957?arnumber=1231957 (A hardware version of LNS in 2003 using Very Long Instruction Word (VLIW).)
  27. Rizalafande Che Ismail, Sep 2012, Fast, area-efficient 32-bit LNS for computer arithmetic operations, Ph.D. Thesis, Newcastle University, https://theses.ncl.ac.uk/jspui/handle/10443/1702, PDF: https://theses.ncl.ac.uk/jspui/bitstream/10443/1702/1/Che%20Ismail%2012.pdf
  28. M.G. Arnold, T.A. Bailey, J.R. Cowles and JJ. Cupal, 1990, Redundant Logarithmic Arithmetic, IEEE Trans Computers, vol. 39, No. 8, pp. 1077-1086, 1990 https://ieeexplore.ieee.org/abstract/document/57046
  29. Joshua Yung Lih Low; Ching Chuen Jong, 2017, Range Mapping—A Fresh Approach to High Accuracy Mitchell-Based Logarithmic Conversion Circuit Design, IEEE Transactions on Circuits and Systems I: Regular Papers ( Volume 65, Issue 1, January 2018) https://ieeexplore.ieee.org/abstract/document/7968344/
  30. D.M. Lewis, 1995, 114 MFLOPS Logarithmic Number System Arithmetic Unit for DSP Applications, IEEE J. Solid-State Circuits, vol. 30, pp 1547-1553,1995 https://ieeexplore.ieee.org/document/482205
  31. D. M. Lewis, 1994, Interleaved memory function interpolators with application to an accurate LNS arithmetic unit, IEEE Trans. Computers, Vol. 43, No. 8, pp.974-982, 1994. https://ieeexplore.ieee.org/document/295859
  32. P Lee, E Costa, S McBader, 2007, LogTOTEM: A logarithmic neural processor and its implementation on an FPGA fabric, 2007 International Joint Conference on Neural Networks, https://ieeexplore.ieee.org/abstract/document/4371396/, PDF: https://www.academia.edu/download/46203834/LogTOTEM_A_Logarithmic_Neural_Processor_20160603-13176-1fohbpz.pdf
  33. Peter Lee, 2007, A VLSI implementation of a digital hybrid-LNS neuron, 2007 International Symposium on Integrated Circuits, https://ieeexplore.ieee.org/document/4441783, PDF: https://www.researchgate.net/profile/Peter-Lee-48/publication/4315642_A_VLSI_implementation_of_a_digital_hybrid-LNS_neuron/links/0c96051dd594f5a004000000/A-VLSI-implementation-of-a-digital-hybrid-LNS-neuron.pdf
  34. Pramod Kumar Meher and Thanos Stouraitis (editors), 15 September 2017. Arithmetic Circuits for DSP Applications, https://www.amazon.com/Arithmetic-Circuits-Applications-Pramod-Kumar/dp/1119206774/
  35. R.C Ismail; M.K Zakaria; S.A.Z Murad, 2013, Hybrid logarithmic number system arithmetic unit: A review, in IEEE ICCAS, Sept 2013, pp. 55–58. https://ieeexplore.ieee.org/document/6671617
  36. Haohuan Fu; Oskar Mencer; Wayne Luk, 2007, Optimizing logarithmic arithmetic on FPGAs, 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007), https://ieeexplore.ieee.org/abstract/document/4297253/, PDF: https://spiral.imperial.ac.uk/bitstream/10044/1/5934/1/optlns.pdf
  37. Barry Lee & Neil Burgess, 2003, A dual-path logarithmic number system addition/subtraction scheme for FPGA, Springer, International Conference on Field Programmable Logic and Applications, FPL 2003: Field Programmable Logic and Application, pp. 808–817, https://link.springer.com/chapter/10.1007/978-3-540-45234-8_78
  38. G Anusha, KC Sekhar, BS Sridevi, 2023, The Journey of Logarithm Multiplier: Approach, Development and Future Scope, In: Recent Developments in Electronics and Communication Systems, KVS Ramachandra Murthy et al. (Eds.) IOS Press, https://ebooks.iospress.nl/pdf/doi/10.3233/ATDE221243, https://www.researchgate.net/publication/367067187_The_Journey_of_Logarithm_Multiplier_Approach_Development_and_Future_ScopeF
  39. B Zerom, M Tolba, H Tesfai, H Saleh, 2022, Approximate Logarithmic Multiplier For Convolutional Neural Network Inference With Computational Reuse, 2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS), https://ieeexplore.ieee.org/document/9970861 (Combines the Logarithmic Number System, Mitchell's approximate multiplication algorithm, and data reuse strategies to speed up MAC operations.)

For more research papers on hardware acceleration issues for LNS models, see https://www.aussieai.com/research/logarithmic#hardware.

 

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